Semiconductor device, semiconductor package and method of manufacturing the same

ABSTRACT

A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korea patent ApplicationNo. 10-2021-0117673 filed on Sep. 3, 2021 in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein byreference in its entirety.

BACKGROUND

Example embodiments of the present disclosure relate to a semiconductordevice, a semiconductor package and a method of manufacturing the same.

There have been efforts to improve integration density of varioussemiconductor packages such as logic circuits and memories. As a methodfor integrating more components (e.g., semiconductor chips) into apackage structure, a stacking technique such as a three dimensionalintegrated circuit (3D IC) has been widely used.

Recently, the 3D IC technique may, by reducing a length ofinterconnection between stacked chips using a direct bonding, have highintegration density, a high processing speed, and a wide bandwidth.Generally, a bonding pad for interconnection has been manufactured usinga damascene process, but it may be difficult to implement high flatnessrequired for direct bonding.

SUMMARY

Example embodiments of the present disclosure is to provide asemiconductor package having improved reliability.

Example embodiments of the present disclosure is to provide asemiconductor chip having improved reliability.

Example embodiments of the present disclosure is to provide a method ofmanufacturing a semiconductor chip having improved reliability.

According to example embodiments of the present disclosure, asemiconductor package includes a first semiconductor chip having a firstsubstrate, a first insulating layer on the first substrate, and aplurality of first bonding pads on the first insulating layer, andhaving a flat upper surface by an upper surface of the first insulatinglayer and upper surfaces of the plurality of first bonding pads; and asecond semiconductor chip on the upper surface of the firstsemiconductor chip and having a second substrate, a second insulatinglayer below the second substrate and in contact with the firstinsulating layer, and a plurality of second bonding pads on the secondinsulating layer and in contact with the first bonding pads,respectively, wherein the first insulating layer includes an insulatinginterfacial layer in contact with the second insulating layer, embeddedin the first insulating layer, and spaced apart from the plurality offirst bonding pads.

According to example embodiments of the present disclosure, asemiconductor package includes a first semiconductor chip having a firstsubstrate, a first insulating layer on the first substrate, and aplurality of first bonding pads on the first insulating layer, andhaving a flat upper surface by an upper surface of the first insulatinglayer and upper surfaces of the plurality of first bonding pads; and asecond semiconductor chip on the upper surface of the firstsemiconductor chip and having a second substrate, a second insulatinglayer below the second substrate and in contact with the firstinsulating layer, and a plurality of second bonding pads on the secondinsulating layer and in contact with the first bonding pads,respectively, wherein the first semiconductor chip includes a protectiveinsulating film between the first substrate and the first insulatinglayer, through electrodes penetrating the first substrate and the firstinsulating layer and connected to the plurality of first bonding pads,respectively, and a first conductive barrier layer and a first seedlayer on the protective insulating film and between the plurality offirst bonding pads and the through electrodes, and wherein the firstconductive barrier layer and the first seed layer are inwardly spacedapart from an outer periphery of each of the plurality of first bondingpads.

According to example embodiments of the present disclosure, asemiconductor chip includes a substrate having a first surface having anactive region and a second surface opposite to the first surface; aninterlayer insulating film on the first surface of the substrate andhaving a wiring structure connected to the active region; a firstpassivation layer on the interlayer insulating film and having firstbonding pads electrically connected to the wiring structure; aprotective insulating film on the second surface of the substrate;through electrodes electrically connected to the wiring structure andpenetrating the substrate and the protective insulating film; a secondpassivation layer on the protective insulating film and having secondbonding pads electrically connected to the through electrode, where eachof the second bonding pads has a width increasing toward the secondsurface of the substrate; and a conductive layer on the protectiveinsulating film and between the second bonding pads and the throughelectrodes, and inwardly spaced apart from an outer periphery of each ofthe second bonding pads.

According to example embodiments of the present disclosure, a method ofmanufacturing a semiconductor chip includes preparing a semiconductorwafer for a plurality of semiconductor chips; forming a photoresistpattern having a plurality of openings on the semiconductor wafer, whereeach of the plurality of openings defines a bonding pad formationregion; forming a plurality of bonding pads in the plurality ofopenings, respectively; removing the photoresist pattern; forming afirst insulating layer on the semiconductor wafer to cover the pluralityof bonding pads; forming a polishing stop film and a second insulatingfilm on the first insulating film, where the first and second insulatingfilms and the polishing stop film are included in a multilayerpassivation; and polishing the multilayer passivation using thepolishing stop film to expose upper surfaces of the plurality of bondingpads.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the presentdisclosure will be more clearly understood from the following detaileddescription, taken in combination with the accompanying drawings, inwhich:

FIG. 1 is a cross-sectional diagram illustrating a semiconductor packageaccording to example embodiments of the present disclosure, viewed fromthe side;

FIG. 2 is an enlarged diagram illustrating portion “A” of thesemiconductor package illustrated in FIG. 1 ;

FIG. 3 is an enlarged diagram illustrating a portion of a semiconductorchip employed in the semiconductor package illustrated in FIG. 2 ;

FIG. 4 is an enlarged diagram illustrating a portion (an interfacialbonding surface between semiconductor chips) of a semiconductor packageaccording to example embodiments of the present disclosure;

FIG. 5 is an enlarged diagram illustrating a portion of a semiconductorchip employed in a semiconductor package according to exampleembodiments of the present disclosure;

FIG. 6 is a cross-sectional diagram illustrating a semiconductor chipaccording to example embodiments of the present disclosure;

FIGS. 7A to 7D are cross-sectional diagrams illustrating main processesof a method of manufacturing a semiconductor chip according to exampleembodiments of the present disclosure;

FIGS. 8A to 8F are cross-sectional diagrams illustrating main processesof a method of manufacturing a semiconductor chip (corresponding to FIG.3 ) according to example embodiments of the present disclosure;

FIGS. 9A and 9B are cross-sectional diagrams illustrating main processesof a method of manufacturing a semiconductor chip (corresponding to FIG.5 ) according to example embodiments of the present disclosure;

FIGS. 10A and 10B are cross-sectional diagrams illustrating mainprocesses of a method of manufacturing a semiconductor chip(corresponding to FIG. 6 ) according to example embodiments of thepresent disclosure;

FIG. 11 is a cross-sectional diagram illustrating a semiconductorpackage according to example embodiments of the present disclosure,viewed from the side; and

FIGS. 12A and 12B are enlarged diagrams illustrating portions “B1” and“B2” of the semiconductor package illustrated in FIG. 11 , respectively.

DETAILED DESCRIPTION

When the terms “about” or “substantially” are used in this specificationin connection with a numerical value, it is intended that the associatednumerical value includes a manufacturing or operational tolerance (e.g.,±10%) around the stated numerical value. Moreover, when the words“generally” and “substantially” are used in connection with geometricshapes, it is intended that precision of the geometric shape is notrequired but that latitude for the shape is within the scope of thedisclosure. Further, regardless of whether numerical values or shapesare modified as “about” or “substantially,” it will be understood thatthese values and shapes should be construed as including a manufacturingor operational tolerance (e.g., ±10%) around the stated numerical valuesor shapes.

Hereinafter, example embodiments of the present disclosure will bedescribed as follows with reference to the accompanying drawings.

FIG. 1 is a cross-sectional diagram illustrating a semiconductor packageaccording to example embodiments. FIG. 2 is an enlarged diagramillustrating portion “A” of the semiconductor package illustrated inFIG. 1 .

Referring to FIGS. 1 and 2 , a semiconductor package 100 may includefirst to fourth semiconductor chips 100A, 100B, 100C, and 100D stackedon a package substrate 50, and/or a molding member 90 surrounding thefirst to fourth semiconductor chips 100A, 100B, 100C, and 100D.

The package substrate 50 may include an upper pad 52 and a lower pad 54disposed on upper and lower surfaces of a substrate body 51,respectively. The substrate body 51 may include an internal wiring (notillustrated) connecting the upper pad 52 to the lower pad 54. Forexample, the package substrate 50 may include a printed circuit board(PCB) or a silicon interposer substrate (an Si interposer substrate).Also, the semiconductor package 100 may further include conductive bumps55 connected to the first semiconductor chip 100A and externalconnection terminals 59 for connection to an external device (e.g., amotherboard).

In example embodiments, the first semiconductor chip 100A may havesubstantially the same structure as or similar to those of the second tofourth semiconductor chips 100B, 100C, and 100D, and the same or similarcomponents may be denoted by the same or similar reference numerals, anddescriptions of the same components need not be repeated. However,differently from the other semiconductor chips, the fourth semiconductorchip 100D disposed in an uppermost portion may not include a throughelectrode and may have a relatively large thickness.

For example, each of the first to third semiconductor chips 100A, 100B,and 100C may include a substrate 110, a wiring structure 120, a throughelectrode 130, a lower bonding pad 145, and/or an upper bonding pad 175.The fourth semiconductor chip 100D disposed on the uppermost portion mayinclude the same components other than the through electrode 130.

The substrate 110 may have a first surface 110 a having an active regionand a second surface 110 b disposed opposite to the first surface. Thefirst surface 110 a and the second surface 110 b may also be referred toas an active surface and an inactive surface, respectively. A pluralityof individual devices 115 such as transistors may be formed on the firstsurface 110 a (the active region) of the substrate 110. An interlayerinsulating film 111 covering the plurality of individual devices 115 maybe formed on the first surface 110 a of the substrate 110, and theplurality of individual devices 115 may be connected to each other by aninterconnection portion 113 (e.g., a contact plug). A wiring structure120 having a low dielectric layer 121 and a plurality of wiring layers125 may be disposed on the interlayer insulating film 111, and thewiring layer 125 may be connected to the plurality of individual devices115 by the interconnection portion 113. The wiring layer 125 may includea multilayer structure including a wiring pattern and a via. Also, thewiring structure 120 may be connected to the through electrode 130. Forexample, as illustrated in FIG. 2 , the wiring layer 125 may include alanding pad 125P connected to the through electrode 130.

The interlayer insulating film 111 or the low dielectric layer 121 maybe flowable oxide (FOX), tonen silazen (TOSZ), undoped silica glass(USG), borosilica glass (BSG), phosphosilaca glass (PSG),borophosphosilica glass (BPSG), plasma enhanced tetra ethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), high density plasma(HDP) oxide, plasma enhanced oxide (PEOX), flowable CVD (FCVD) oxide, ora combination thereof. The interlayer insulating film 111 or the lowdielectric layer 121 may be formed using a chemical vapor deposition(CVD), a flowable-CVD process, or a spin coating process.

Referring to FIG. 2 , an insulating protective layer 157 disposed on thesecond surface 110 b of the substrate 110 may be included, and thethrough electrode 130 may be configured to penetrate the substrate 110,the interlayer insulating film 111, and the insulating protective layer157. The through electrode 130 may include a via plug 135 and a sideinsulating layer 131 surrounding a side surface of the via plug 135. Theside insulating layer 131 may electrically isolate the via plug 135 fromthe substrate 110.

A lower insulating layer 141 disposed on the lower surface of each ofthe first to fourth semiconductor chips 100A, 100B, 100C, and 100D, thatis, disposed on the wiring structure 120, and a lower bonding pad 145disposed on the lower insulating layer 141 and connected to the wiringlayer 125 may be included. Also, an upper insulating layer 171 disposedon the upper surface of each of the first to third semiconductor chips100A, 100B, and 100C, that is, on the insulating protective layer 157,and an upper bonding pad 175 disposed on the upper insulating layer 171and connected to the through electrode 130 may be included. In each ofthe first to third semiconductor chips 100A, 100B, and 100C, the upperand lower bonding pads 145 and 175 may be vertically connected to eachother together with the wiring layer 125 by the through electrode 130.

In example embodiments, the first to fourth semiconductor chips 100A,100B, 100C, and 100D may be stacked by hybrid bonding. As illustrated inFIG. 2 , as for the bonding of the first and second semiconductor chips100A and 100B, an intermetallic interfacial bonding surface BS1 by thelower connecting pad 145 and the upper connecting pad 175 may becombined with an inter-dielectric interfacial bonding surface BS2between the lower insulating layer 141 and the upper insulating layer171 such that a hybrid interfacial bonding surface BS may be formed.Similarly, bonding of the second and third semiconductor chips 100B and100C and the third and fourth semiconductor chips 100C and 100D may beimplemented.

For example, as illustrated in FIG. 2 , the upper bonding pad 175 of thefirst semiconductor chip 100A may be directly bonded to the lowerbonding pad 145 of the second semiconductor chip 100B such that anelectrical connection between the first and second semiconductor chips100A and 100B and bonding between the first and second semiconductorchips 100A and 100B may be implemented.

The lower bonding pad 145 and the upper bonding pad 175 may include thesame metal, such as, for example, copper (Cu). The lower bonding pad 145and the upper bonding pad 175, directly bonded to each other, may bebonded by copper interdiffusion through a high-temperature annealingprocess. The metal forming the lower bonding pad 145 and the upperbonding pad 175 is not limited to copper, and may include other metalmaterials (e.g., Au) which may implement the bonding as above.Electrical connection may be implemented by the strong bonding betweenthe stacked semiconductor chips through the metal bonding and also thedirect-bonding without a connection bump. A path for transmitting andreceiving at least one of a control signal, a power signal, a groundsignal, and a data signal between the first to fourth semiconductorchips 100A, 100B, 100C, and 100D may be provided. Since a connectionbump such as solder is not used, transmission loss may be reduced.

Also, the upper insulating layer 171 disposed on the upper surface ofeach of the first to third semiconductor chips 100A, 100B, and 100C maybe directly bonded to the lower insulating layers 141 disposed on thelower surface of each of the second to fourth semiconductor chips 100B,100C, and 100D. The upper insulating layer 171 and the lower insulatinglayer 141 may include the same material or similar materials. The upperinsulating layer 171 in example embodiments may include an insulatinginterfacial layer 179 in contact with the lower insulating layer 141 andembedded in the upper insulating layer 171. The insulating interfaciallayer 179 may include a material different from that of the upperinsulating layer 171.

As illustrated in FIG. 3 , the insulating interfacial layer 179 inexample embodiments may be a component of the first semiconductor chip100A, and may be formed on the upper insulating layer 171 of the firstsemiconductor chip 100A and may be provided as a bonding surface withthe lower insulating layer 141 of the second semiconductor chip 100B.

The insulating interfacial layer 179 may be spaced apart from the upperbonding pad 175 on the upper surface of the upper insulating layer 171.This separation may be caused by a multilayer passivation employed for aplanarization process (see FIGS. 8E and 8F). The insulating interfaciallayer 179 may be a remaining portion of the polishing stop film of themultilayer passivation. In example embodiments, a distance d2 by whichthe insulating interfacial layer 179 is spaced apart from the upperbonding pad 175 may be in the range of 60% to 100% of the thickness ofthe upper bonding pad 175.

For example, the upper insulating layer 171 and the lower insulatinglayer 141 may include silicon oxide. The insulating interfacial layer179 may include at least one of silicon nitride (SiN), silicon carbide(SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminumnitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO) andaluminum oxide carbide (AlOC). In example embodiments, the upperinsulating layer 171 and the insulating interfacial layer 179 mayinclude the same material having different polishing properties. Forexample, the upper insulating layer 171 may be porous silicon oxide, andthe insulating interfacial layer 179 may be silicon oxide deposited byanother process such as CVD.

The direct bonding between the upper insulating layer 171 (inparticular, the insulating interfacial layer 179) and the lowerinsulating layer 141 may be performed by applying a high-temperatureannealing process while the two insulating layers 141 and 171 are indirect contact with each other. The bonding may ensure stronger bondingstrength by covalent bonding.

The upper bonding pad 175 in example embodiments may be formed by aprocess different from the process of forming the lower bonding pad 145.For example, the lower bonding pad 145 may be formed by a generaldamascene process, whereas the upper bonding pad 175 may be formed by anew method disclosed herein, that is, a photoresist process and aplanarization process using a polishing stop film (or the insulatinginterfacial layer 179). The upper bonding pad 175 formed by the newprocess may have structural properties different from that of the lowerbonding pad 145.

As illustrated in FIG. 2 , the lower bonding pad 145 may have a widthincreasing toward the interfacial bonding surface BS, whereas the upperbonding pad 175 in example embodiments may have a width decreasingtoward the interfacial bonding surface BS. As for the lower bonding pad145, the lower insulating layer 141 may be formed in advance, and anopening for the pad may be formed, and thereafter, the conductivebarrier layer 142 may be formed in the opening, and the lower bondingpad 145 may be formed using a plating process. The conductive barrierlayer 142 may include at least one of titanium (Ti), titanium nitride(TiN), tantalum (Ta), and tantalum nitride (TaN).

Differently from the above example, the upper bonding pad 175 may have aside surface 175S inclined toward the interfacial bonding surface BS,and a capping barrier film 167 may be formed on the side surface 175S ofthe upper bonding pad 175. The capping barrier film 167 in exampleembodiments may be an insulating material. The capping barrier film 167may include a material the same as or similar to that of the insulatinginterfacial layer 179. For example, the capping barrier film 167 mayinclude at least one of silicon nitride (SiN), silicon carbide (SiC),silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride(AlN), aluminum oxynitride (AlON), aluminum oxide (AlO) and aluminumoxide carbide (AlOC). In example embodiments, the thickness of thecapping barrier film 167 may be in a range of 100-300 nm.

As illustrated in FIGS. 2 and 3 , an extended barrier film 167R formedof the same material as that of the capping barrier film 167 may beformed on the protective insulating film 151. A buffer film 157 such asa polishing stop film or a barrier may be disposed on the upper surfaceof the protective insulating film 151. For example, the buffer film 157may include silicon nitride, silicon carbide, silicon oxynitride, orsilicon carbonitride.

In some example embodiments, the capping barrier film 167 and theextension barrier film 167R disposed on the side surface 175S of theupper bonding pad 175 may be separated from each other, but in otherexample embodiments, the capping barrier film 167 may be continuouslyformed to be connected to the extended barrier film 167R.

A conductive barrier layer 162 and a seed layer 164 may be disposed onthe lower surface 175U of the upper bonding pad 175. For example, asillustrated in FIGS. 2 and 3 , the conductive barrier layer 162 and theseed layer 164 may be sequentially disposed on the protective insulatingfilm 151 to be positioned in a region between the upper bonding pad 175and the through electrode 130. In particular, the conductive barrierlayer 162 and the seed layer 164 may have an undercut structure UC,inwardly spaced apart from the outer periphery of the upper bonding pad175. A distance d1 by which the conductive barrier layer 162 and theseed layer 164 are spaced apart from the outer periphery of the upperbonding pad 175 may be in the range of 1% to 15% of the width (withrespect to the width of a lower end) of the upper bonding pad 175, andin example embodiments, in the range of 2% to 10% of the width. Forexample, the conductive barrier layer 162 may include at least one oftitanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalumnitride (TaN). For example, the seed layer 164 may include copper (Cu),chromium-copper (Cr—Cu), palladium (Pd), platinum (Pt), gold (Au), or acombination thereof. In example embodiments, the seed layer 164 mayinclude Cu. For example, the lower and upper bonding pads 145 and 175may include copper (Cu), chromium-copper (Cr—Cu), palladium (Pd),platinum (Pt), or gold (Au), and in example embodiments, the lower andupper bonding pads 145 and 175 may include Cu. For example, thethickness of the first conductive barrier layer 162 may be in the rangeof 100-250 nm, and the thickness of the first seed layer 164 may be inthe range of 50-150 nm.

As illustrated in FIG. 2 , the upper bonding pad 175 may have an uppersurface 175T substantially coplanar with the upper surface 171T of theupper insulating layer 171. In particular, in example embodiments, theupper surface 175T of the upper bonding pad 175 may be substantiallycoplanar with the upper surface of the insulating interfacial layer 179embedded in the upper insulating layer 171.

As such, the hybrid bonding in example embodiments may be implemented bythe metal bonding structure for directly bonding the upper bonding pad175 to the lower bonding pad 145, and the dielectric bonding structurefor directly bonding the upper insulating layer 171 (in particular, theinsulating interfacial layer 179) to the lower insulating layer 141.Also, the bonding between the second and third semiconductor chips 100Band 100C and the bonding between the third and fourth semiconductorchips 100C and 100D may also be implemented by the hybrid bondingdescribed with reference to FIG. 2 .

The first to fourth semiconductor chips 100A, 100B, 100C, and 100D maybe a memory chip or a logic chip. In example embodiments, the first tofourth semiconductor chips 100A, 100B, 100C, and 100D may be the sametype of memory chip, and in another example, a portion of the first tofourth semiconductor chips 100A, 100B, 100C, and 100D may be memorychips, and the other portion may be logic chips.

For example, the memory chip may be a volatile memory chip such as adynamic random access memory (DRAM) or a static random access memory(SRAM), or may be a non-volatile memory chip such as a phase-changerandom access memory (PRAM), a magnetic random access memory (MRAM), aferroelectric random access memory (FeRAM), or a resistive random accessmemory (RRAM). In example embodiments, the first to fourth semiconductorchips 100A, 100B, 100C, and 100D may be high bandwidth memory (HBM)DRAMs.

In example embodiments, the first to fourth semiconductor chips 100A,100B, 100C, and 100D may be stacked on the package substrate 500. Thesemiconductor package according to example embodiments may include thefour same semiconductor chips 100A, 100B, 100C, and 100D as a multi-chippackage, but example embodiments thereof are not limited thereto, andthe semiconductor package may include a different number ofsemiconductor chips, and different types of semiconductor chips may bestacked (see FIGS. 11 and 12 ).

FIG. 4 is an enlarged diagram illustrating a portion (an interfacialbonding surface between semiconductor chips) of a semiconductor packageaccording to example embodiments. FIG. 5 is an enlarged diagramillustrating a semiconductor chip employed in the semiconductor package,a portion of a semiconductor package, according to example embodiments.

FIG. 4 illustrates a portion corresponding to portion A in FIG. 1similarly to FIG. 2 , and FIG. 5 may be an enlarged diagram illustratinga single semiconductor chip (before bonding) similarly to FIG. 3 .

Referring to FIGS. 4 and 5 , a semiconductor package 100′ according toexample embodiments may have a structure similar to that of thesemiconductor package 100 illustrated in FIGS. 1 to 3 other than theconfiguration in which the structure of the lower bonding pad 145 of thesecond semiconductor chip 100B′ may be different, and the insulatinginterfacial layer 179 (in FIG. 2 ) is not provided. The descriptions ofthe same or similar components of the semiconductor package 100illustrated in FIGS. 1 to 3 will be applied to the components in exampleembodiments unless otherwise indicated.

The lower bonding pad 145 in example embodiments may be formed by aprocess similar to the process of forming the upper bonding pad 175. Asillustrated in FIG. 4 , the lower bonding pad 145 may have a widthdecreasing toward the interfacial bonding surface. That is, the lowerbonding pad 145 may have a side surface inclined toward the interfacialbonding surface, and a capping barrier film 147 may be formed on theside surface of the lower bonding pad 145. As for the capping barrierfilm 147, an extended barrier film 147R formed of the same material asthat of the capping barrier film 147 may be formed on the wiringstructure 120.

A conductive barrier layer 142 and a seed layer 144 may be disposed on alower surface of the lower bonding pad 145. The conductive barrier layer142 and the seed layer 144 may be disposed in order on the wiringstructure 120 below the lower bonding pad 145. Also, the conductivebarrier layer 142 and the seed layer 144 may have an undercut structure,inwardly spaced apart from the outer periphery of the lower bonding pad145. A distance da by which the conductive barrier layer 142 and theseed layer 145 are spaced apart from the outer periphery of the lowerbonding pad 145 may be in the range of 1% to 15% of the width (withrespect to the width of the upper end) of the lower bonding pad 145, andmay be in the range of 2% to 10% of the width in example embodiments.The lower bonding pad 145 may have an upper surface substantiallycoplanar with the upper surface of the lower insulating layer 141.

As illustrated in FIG. 4 , an insulating interfacial layer may not beprovided on the interfacial bonding surface between the upper insulatinglayer 175 and the lower insulating layer 145 in example embodiments. Asillustrated in FIG. 5 , the bonding surface of the first semiconductorchip 100A′ may be provided by the upper bonding pad 175 and the upperinsulating layer 171. That is, differently from example embodimentsillustrated in FIG. 3 , the bonding surface may be provided by thesurface of the upper insulating layer 171 without an insulatinginterfacial layer.

FIG. 6 is a cross-sectional diagram illustrating a semiconductor chipaccording to example embodiments. FIG. 6 is an enlarged diagramillustrating a single semiconductor chip (before bonding) similarly toFIGS. 3 and 5 .

Referring to FIG. 6 , a semiconductor chip 100A″ according to exampleembodiments may have a structure similar to that of the semiconductorchip 100A illustrated in FIG. 3 other than the configuration in whichthe capping barrier film 168 may be a conductive material and theformation position thereof may be different. The descriptions of thesame or similar components of the semiconductor package 100A illustratedin FIG. 3 will be applied to the components in example embodimentsunless otherwise indicated.

The capping barrier film 168 in example embodiments may include aconductive material. For example, the capping barrier film 168 mayinclude at least one of copper silicide (CuSi_(x)), titanium silicide(TiSi_(x)), CuSiN, cobalt (Co), tungsten (W), palladium (Pd), gold (Au),and nickel (Ni).

The capping barrier film 168 may be formed on the side surface of theupper bonding pad 175 and also on the upper surface. Since the cappingbarrier film 168 is formed of a conductive material, the capping barrierfilm 168 also may remain on the upper surface of the upper bonding pad175, which may be the surface bonded to the lower bonding pad 145. Inexample embodiments, the capping barrier film 168 may be formed onalmost the entire upper surface of the upper bonding pad 175, and aportion disposed on the upper surface may have a thickness less than athickness of a portion disposed on the side surface. In other exampleembodiments, the capping barrier film 168 may remain in a partial regionof the upper surface of the upper bonding pad 175. Also, the cappingbarrier film 168 may be formed only on the surface of the upper bondingpad 175 using a selective film formation process (e.g., electrolyticplating). Accordingly, in the first semiconductor chip 100A″ accordingto example embodiments, differently from the aforementioned exampleembodiments, the extended barrier film portion 167R (in FIG. 3 )disposed on the protective insulating film 151 may not be provided.

FIGS. 7A to 7D are cross-sectional diagrams illustrating main processesof a method of manufacturing a semiconductor chip according to exampleembodiments. The manufacturing method according to example embodimentsmay be the method of manufacturing the first semiconductor chip 100Adescribed with reference to FIGS. 1 to 3 .

Referring to FIG. 7A, a semiconductor wafer 100W for a plurality ofsemiconductor chips 100A may be temporarily bonded to be supported by acarrier substrate 510 using a bonding material layer 520.

In this process, the semiconductor wafer 100W may be bonded such thatthe active surface side of the semiconductor wafer 100W may oppose thecarrier substrate, and the semiconductor wafer 100W may be stablysupported by the adhesive material layer 520 such as glue during asubsequent process. The semiconductor wafer 100W may include componentsfor the first semiconductor chip 100A. For example, the throughelectrode 130 may be formed on the active surface of the semiconductorwafer together with the device region, the wiring structure 120, and thelower bonding pad 145. As for the through electrode 130, thesemiconductor wafer 100W may be formed in advance before or whileforming the device region, and the through electrode 130 may have adepth greater than the thickness of a final semiconductor chip from theactive surface (the through electrode 130 may not entirely penetrate thewafer).

Referring to FIG. 7B, the thickness of the semiconductor wafer 100W maybe reduced by applying a polishing process to the upper surface(inactive surface) of the semiconductor wafer 100W.

In this process, by removing a portion of the semiconductor wafer 100W,the upper end 130T′ of the through electrode 130 may protrude from theupper surface of the semiconductor wafer 100W. Through this polishingprocess, the thickness of the semiconductor wafer 100W may be reduced toa desired thickness of the first semiconductor chip 100A. For thisprocess, a grinding process such as a chemical mechanical polishing(CMP) process, an etch-back process, or a combination thereof may beused. For example, in this process, the thickness of the semiconductorwafer 100W may be reduced to a predetermined or alternatively, desiredthickness by performing a grinding process, and the through electrode130 may be sufficiently exposed by applying the etch-back underappropriate conditions.

Thereafter, referring to FIG. 7C, a protective insulating film 151 and abuffer film 157 may be formed in order on the upper surface of thesemiconductor wafer 100W to cover the exposed upper end 130T of thethrough electrode 130. Thereafter, referring to FIG. 7D, the protectiveinsulating film 151 and the buffer film 157 may be ground to expose thethrough electrode 130.

The protective insulating film 151 may be silicon oxide, and the bufferfilm 157 may be silicon nitride or silicon oxynitride. A grindingprocess may be performed up to a predetermined or alternatively, desiredline GL1 such that the insulating layer protective film 151 and thebuffer film 157 may be partially removed and the through electrode 130may be exposed. Through this grinding process, the protective insulatingfilm 151 may have an upper surface substantially coplanar with the uppersurface of the through electrode 130. Also, a damaged portion of theupper end 130T of the through electrode 130 may be removed.

FIGS. 8A to 8F are cross-sectional diagrams illustrating main processesof a method of manufacturing a semiconductor chip (corresponding to FIG.3 ) according to example embodiments.

The portion illustrated in FIG. 8A may correspond to the portionillustrated in FIG. 3 , and may correspond to a portion of thewafer-level first semiconductor chip 100A manufactured in FIG. 7D. Also,the subsequent processes may be wafer level processes in FIGS. 7A to 7Dand may be consecutively performed.

Referring to FIG. 8B, a conductive barrier layer 162 and a seed layer164 may be sequentially formed on the protective insulating film 151.

The conductive barrier 162 layer may be provided as a barrier to reduceor prevent diffusion of a metal component such as Cu before the seedlayer 164 is formed, and the seed layer 164 may be used as a seed forthe plating process to form the upper bonding pad 175 (in FIG. 8C). Forexample, the conductive barrier layer 162 may include at least one oftitanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalumnitride (TaN). For example, the seed layer 164 may include copper (Cu),chromium-copper (Cr—Cu), palladium (Pd), platinum (Pt), gold (Au), or acombination thereof. In example embodiments, the seed layer 164 mayinclude Cu.

Thereafter, referring to FIG. 8C, a photoresist pattern PR having anopening may be formed on the semiconductor wafer 100W, and the upperbonding pad 175 may be formed in the opening.

In example embodiments, the opening may be provided to define aformation region of the bonding pad, and a desired opening may be formedthrough an exposure/development process after the photoresist layer isformed. The opening may have a space of which a width decreasesupwardly. The upper bonding pad 175 may be formed on the region of theseed layer 164 exposed through the opening using an electroplatingprocess. The side surface 175S of the upper bonding pad 175 may have asurface inclined inwardly. For example, the upper bonding pad 175 mayinclude Cu. The upper bonding pad 175 formed in this process may have anon-flat upper surface 175T (a slightly convex upper surface), and mayhave a flat surface in a subsequent grinding process.

Thereafter, referring to FIG. 8D, the photoresist pattern PR may beremoved, and exposed portions of the conductive barrier layer 162 andthe seed layer 164 may be removed.

The photoresist pattern PR may be removed using an ashing process. Afterthe photoresist pattern PR is removed, the exposed portions of theconductive barrier layer 162 and the seed layer 164 may be etched. Inthis etching process, a region disposed below the upper bonding pad 175may be partially etched. Accordingly, the remaining portions of theconductive barrier layer 162 and the seed layer 164 may have an undercutstructure UC, inwardly spaced apart from the outer periphery of theupper bonding pad 175. A distance by which the conductive barrier layer162 and the seed layer 165 are spaced apart from the outer periphery ofthe upper bonding pad 175 may be in the range of 1% to 15% of the width(with respect to the width of the lower end) of the upper bonding pad175, and may be may in the range of 2% to 10% of the width in exampleembodiments.

Thereafter, referring to FIG. 8E, a capping barrier film 167L may beformed, and a first insulating film 171 a may be formed to cover theupper bonding pad 175.

The capping barrier film 167L may be used as a barrier between the upperbonding pad 175 and the first insulating film 171 a. As illustrated, thecapping barrier film 167L may be formed on the upper surface 175T′ andthe side surface 175S of the upper bonding pad 175 and may almostcontinuously formed on the protective insulating film 151. In exampleembodiments, the level L2 of the upper surface of the first insulatingfilm 171 a may be relatively lower than the level L1 (the lowest level)of the upper surface of the upper bonding pad 175. The level of thepolishing stop film 179 to be formed in a subsequent process may bedetermined by the thickness t1 of the first insulating film 171 a.

Thereafter, referring to FIG. 8F, a polishing stop film 179 and a secondinsulating film 171 b may be formed in order on the first insulatingfilm 171 a.

The polishing stop film 175 and the second insulating film 171 b may beincluded in a multilayer passivation MP together with the firstinsulating film 171 a. In a subsequent process, the multilayerpassivation MP may be polished using the polishing stop layer 179 suchthat the upper surface 175T of the upper bonding pad 175 may be exposed.In example embodiments, the polishing may be performed up to line “GL2,”such that a capping barrier film portion of the upper surface 175T ofthe upper bonding pad 175 may be removed and the upper surface thereofmay be planarized. Also, the upper surface of the upper bonding pad 175may be substantially coplanar with the upper surface of the remainingmultilayer passivation MP.

By appropriately adjusting the upper surface level L2 of the firstinsulating film in the previous process, the upper surface of themultilayer passivation MP may be provided by the polishing stop film 179in example embodiments. In example embodiments, the remaining polishingfilm 179 may also be referred to as an “insulating interfacial layer” asdescribed above. The remaining polishing stop film 179 may be embeddedin the upper insulating layer 171 and may provide a bonding surface, andmay be spaced apart from the upper bonding pad 175. In exampleembodiments, the distance d2 by which the remaining polishing stop layer179 is spaced apart from the upper bonding pad 175 may be in a range of60% to 100% of the thickness of the upper bonding pad 175.

FIGS. 9A and 9B are cross-sectional diagrams illustrating main processesof a method of manufacturing a semiconductor chip (corresponding to FIG.5 ) according to example embodiments. The process illustrated in FIG. 9Aaccording to example embodiments may be understood as a subsequentprocess of the process in FIG. 8D.

Referring to FIG. 9A, a capping barrier film 167L may be formed on thesurface of the upper bonding pad 175, and a first insulating film 171 aand a polishing stop film 179 may be formed to cover the upper bondingpad 175.

In example embodiments, the first insulating film 171 a may have athickness t2 relatively larger than the thickness t1 of the firstinsulating film described in the aforementioned example embodiments.That is, the level L2′ of the upper surface of the first insulating film171 a may be relatively higher than the level L1 (the lowest level) ofthe upper surface of the upper bonding pad 175. Accordingly, thepolishing stop film 175 may be disposed on a level relatively higherthan the level L1 of the upper surface of the upper bonding pad 175 (seethe first semiconductor chip 100A in FIG. 3 ).

Thereafter, referring to FIG. 9B, a second insulating film 171 b may beformed on the polishing stop film 179, and a multilayer passivation (MP)may be polished up to line “GL2′” using the polishing stop film 179.

Through this polishing process, the upper surface 175T of the upperbonding pad 175 may be planarized, and simultaneously, the upper surfaceof the upper bonding pad 175 may be substantially coplanar with theupper surface of the remaining multilayer passivation MP. Also, thepolishing stop film 179 may be entirely removed, such that, differentlyfrom the previous embodiments, the upper insulating layer 171 may beprovided as a bonding surface (see the first semiconductor chip 100A′ inFIG. 5 ).

FIGS. 10A and 10B are cross-sectional diagrams illustrating mainprocesses of a method of manufacturing a semiconductor chip(corresponding to FIG. 6 ) according to example embodiments. The processillustrated in FIG. 10A according to example embodiments may beunderstood as a subsequent process of the process in FIG. 8D.

Referring to FIG. 10A, a capping barrier film 168 may be formed on thesurface of the upper bonding pad 175.

The capping barrier film 168 in example embodiments may be a conductivematerial. The capping barrier film 168 may be formed only on the uppersurface 175T and the side surface 175S of the upper bonding pad 175, andmay not be formed on the protective insulating film 151. The cappingbarrier film 168 may be formed by a selectively film forming process,such as, for example, an electrolytic plating process. For example, thecapping barrier film 168 may include at least one of copper silicide(CuSi_(x)), titanium silicide (TiSi_(x)), CuSiN, cobalt (Co), tungsten(W), palladium (Pd), gold (Au), and nickel (Ni).

Thereafter, referring to FIG. 10B, a first insulating film 171 a may beformed to cover the upper bonding pad 175, a polishing stop film 179 anda second insulating film 171 b may be formed in order on the firstinsulating film 171 a, and the multilayer passivation MP may be polishedup to the “GL3′” line using the polishing stop film 179.

After the polishing process, the capping barrier film 168 may alsoremain on the upper surface of the upper bonding pad 175. Since thecapping barrier film 168 in example embodiments is a conductivematerial, the capping barrier film 168 may not interfere with electricalconnection. The capping barrier film 168 formed in this process may beformed on almost the entire upper surface of the upper bonding pad 175,and a portion disposed on the upper surface may have a thickness lessthan a thickness of a portion disposed on the side surface (see thefirst semiconductor chip 100A″ in FIG. 6 ). In other exampleembodiments, the capping barrier film 168 may remain only on a partialregion of the upper surface of the upper bonding pad 175.

FIG. 11 is a cross-sectional diagram illustrating a semiconductorpackage according to example embodiments. FIGS. 12A and 12B are enlargeddiagrams illustrating portions “B1” and “B2” of the semiconductorpackage illustrated in FIG. 11 , respectively.

Referring to FIGS. 12A and 12B together with FIG. 11 , a semiconductorpackage 500 according to example embodiments may include first to thirdsemiconductor chips 200, 300, and 400 stacked on a package substrate550. The package substrate 550 may include an upper pad 552, a lower pad554 and an internal wiring (not illustrated) connecting the upper pad552 to the lower pad 554. For example, the package substrate 550 mayinclude a printed circuit board or a silicon interposer substrate. Also,the semiconductor package 500 may further include conductive bumps 555connected to the first semiconductor chip 200 and external connectionterminals 559 connected to an external device.

Differently from example embodiments illustrated in FIG. 1 , the firstto third semiconductor chips 200, 300, and 400 in example embodimentsmay be configured as chips for performing other functions.

The first semiconductor chip 200 may have a front surface 200 a and arear surface 200 b. The first semiconductor chip 200 may include asubstrate 210 such as silicon (Si) having an active surface 210 a and aninactive surface 210 b disposed opposite to the active surface 210 a.The first semiconductor chip 200 may include a first integrated circuitDS1 formed on the active surface 210 a of the substrate. The firstintegrated circuit DS1 may include an electronic device such as atransistor. In example embodiments, the first integrated circuit DS1 mayform a memory device. For example, the first semiconductor chip 200 maybe a memory chip such as a DRAM, an SRAM, an MRAM, or a flash memory.

The first semiconductor chip 200 may include a first wiring structure220 disposed on the active surface 210 a side of the first substrate210. The first wiring structure 220 may include a first dielectric layer221 and a first wiring layer 225. A first insulating layer 241 and firstbonding pads 245 connected to the first wiring layer 225 may be includedon the first wiring structure 220. For example, the first bonding pads245 may be disposed in the first insulating layer 241, and the uppersurface of the first insulating layer 241 and the upper surface of thefirst bonding pads 245 may provide a bonding surface 200 a coplanar withthe upper surfaces mentioned above. The first wiring layer 225 may beconnected to the first integrated circuit DS1 of the first semiconductorchip 200, and may be connected to the first bonding pads 245. The firstwiring layer 225 and the first bonding pads 245 may include a conductivematerial such as metal. The first insulating layer 241 may include aninsulating material such as silicon oxide (SiO).

The first semiconductor chip 200 may include first through electrodes230. The first through electrodes 230 may vertically penetrate the firstsemiconductor chip 200. The first through electrodes 230 may beconnected to the first wiring layer 225. The first through electrodes230 may extend toward the rear surface 200 b of the first semiconductorchip 200 and may be exposed to the rear surface 200 b of the firstsemiconductor chip 200. The first rear pads 275 may be provided on therear surface 200 b of the first semiconductor chip 200 and may beconnected to the first through electrodes 230.

The first semiconductor chip 200 may be mounted on the package substrate550. As illustrated in FIG. 11 , the first semiconductor chip 200 may bedisposed to be faced-up on the package substrate 550. For example, thefirst semiconductor chip 200 may be disposed such that the rear surface200 b may face the package substrate 550, and the first semiconductorchip 200 may be electrically connected to the package substrate 550. Thefirst semiconductor chip 200 may be mounted on the substrate package 550by a flip chip method. For example, connection terminals 555 may beprovided between the first rear pads 240 provided on the rear surface200 b of the first semiconductor chip 200 and the upper pads 552 of thepackage substrate 550.

The second semiconductor chip 300 may be disposed on the firstsemiconductor chip 200. The second semiconductor chip 300 may include asubstrate 310 such as silicon (Si) having an active surface 310 a and aninactive surface 310 b opposite to the active surface. The secondsemiconductor chip 300 may include a passive element (not illustrated),but example embodiments thereof are not limited thereto. For example,the passive element may be a capacitor device, a resistor device, or aninductor device. The second semiconductor chip 300 may have a frontsurface 300 a and a rear surface 300 b. For example, the secondsemiconductor chip 300 may include a second wiring structure 320disposed on the active surface 310 a side of the substrate 310. Thesecond wiring structure 320 may include a second dielectric layer 321and a second wiring layer 325. A first insulating layer 341 and secondbonding pads 345 connected to the second wiring layer 325 may beincluded on the second wiring structure 320. For example, the secondbonding pads 345 may be disposed in the first insulating layer 341, andthe upper surface of the first insulating layer 341 and the uppersurface of the second bonding pads 345 may provide a bonding surface 300a coplanar with the upper surfaces mentioned above. The second wiringlayer 325 may be connected to the second integrated circuit DS2 of thesecond semiconductor chip 300, and may be connected to the secondbonding pads 345. The second wiring layer 325 and the second bondingpads 345 may include a conductive material such as metal. The secondinsulating layer 341 may include an insulating material such as siliconoxide (SiO). The second semiconductor chip 300 may include secondthrough electrodes 330. The second through electrodes 330 may verticallypenetrate the second semiconductor chip 300. The second throughelectrodes 330 may be connected to the second wiring layer 325. Thesecond through electrodes 330 may extend toward the rear surface 300 bof the second semiconductor chip 300 and may be exposed to the rearsurface 300 b of the second semiconductor chip 300.

The second semiconductor chip 300 may be mounted on the firstsemiconductor chip 200. As illustrated in FIG. 11 , the secondsemiconductor chip 300 may be disposed to be faced-up on the firstsemiconductor chip 200. For example, the second semiconductor chip 300may be disposed such that the rear surface 300 b of the secondsemiconductor chip 300 may face the first semiconductor chip 200. Insome example embodiments, the rear surface 300 b of the secondsemiconductor chip 300 may be in contact with the front surface 200 a ofthe first semiconductor chip 200. For example, the rear surface 300 b ofthe second semiconductor chip 300 may be in contact with the firstinsulating layer 241 and the front surface 200 a provided by the firstbonding pads.

As illustrated in FIG. 12B, the second semiconductor chip 300 may bebonded to the first semiconductor chip 200. For example, the firstbonding pads 245 of the first semiconductor chip 200 may be bonded tothe second through electrodes 330 of the second semiconductor chip 300on the boundary between the first semiconductor chip 200 and the secondsemiconductor chip 300.

Similarly to the bonding structures in the aforementioned exampleembodiments, each of the first bonding pads 245 may have a side inclinedtoward the front surface 300 a, and a capping barrier film 247 may bedisposed on the inclined side surface. A first conductive barrier layer242 and a first seed layer 244 may be disposed between the first bondingpads 245 and the first interconnection structure 220. The firstconductive barrier layer 242 and the first seed layer 244 may have anundercut structure, inwardly spaced apart from the outer periphery ofeach of the first bonding pads 245.

The first bonding pads 245 and the second through electrodes 330 mayform an intermetallic interfacial bonding surface BS1. As such, thefirst bonding pads 245 may be directly bonded to the second throughelectrodes 330 of the second semiconductor chip 300 even without abonding pad structure. For example, the first bonding pads 225 and thesecond through-electrodes 330 may be formed of the same material (e.g.,copper (Cu)), such that the interfacial surface between the firstbonding pads 245 and the second through electrode 330 may not bedistinct. The second semiconductor chip 300 and the first semiconductorchip 200 may be electrically connected to each other through the firstbonding pads 245 and the second through electrodes 330. In exampleembodiments, the second through electrodes 330 and the first bondingpads 245 may be bonded to each other using the intermetallic bondinghaving a strong bonding force, and accordingly, structural stability ofthe semiconductor package 500 may improve.

Referring to FIGS. 11 and 12A, the third semiconductor chip 400 may bedisposed on the second semiconductor chip 300. The third semiconductorchip 400 may be a substrate 410 having a front surface 400 a and a rearsurface 400 b, and having an active surface 410 a and an inactivesurface 410 b disposed opposite to each other. The third semiconductorchip 400 may include a third integrated circuit DS3. The thirdintegrated circuit DS3 may include an electronic device such as atransistor. For example, the third integrated circuit DS3 may be a logicdevice. That is, the third semiconductor chip 400 may be a logic chip.For example, the third semiconductor chip 400 may include a thirdinterconnection structure 420 disposed on the active surface 410 a side.The third wiring structure 420 may include a third dielectric layer 421and a third wiring layer 425. A third insulating layer 441 may be formedon the third interconnection structure 420, and third bonding pads 445connected to the third interconnection layer 425 may be disposed on thethird insulating layer 441. Lower surfaces of the third bonding pads 445may be coplanar with one surface of the third insulating layer 441. Thethird bonding pads 445 may be connected to the third integrated circuitDS3 of the third semiconductor chip 400 through the third wiring layer425. The third wiring layer 425 and the third bonding pads 445 mayinclude a conductive material such as metal. The third insulating layer441 may include an insulating material such as silicon oxide (SiO).

The third semiconductor chip 400 may be mounted on the secondsemiconductor chip 300. As illustrated in FIG. 12A, the thirdsemiconductor chip 400 may be disposed to be faced-down on the secondsemiconductor chip 300. For example, as for the third semiconductor chip400, the front surface 400 a of the third semiconductor chip 400 mayface the second semiconductor chip 300. In some example embodiments, thefront surface 400 a of the third semiconductor chip 400 may be incontact with the front surface 300 a of the second semiconductor chip300. For example, the third bonding pads 445 of the third semiconductorchip 400 and the second bonding pads 345 of the second semiconductorchip 300 may be in contact with each other.

Similarly to the bonding structure in the aforementioned exampleembodiments, the second bonding pads 345 and the third bonding pads 445may have side surfaces inclined toward the front surfaces 300 a and 400a, respectively, and capping barrier films 347 and 447 may be disposedon the inclined side surfaces, respectively. A second conductive barrierlayer 344 and a second seed layer 342 may be disposed between the secondbonding pads 345 and the second interconnection structure 320. Thesecond conductive barrier layer 344 and the second seed layer 342 mayhave an undercut structure, inwardly spaced apart from the outerperiphery of each of the second bonding pads 345.

Similarly, in the third semiconductor chip 400, a third conductivebarrier layer 442 and a third seed layer 442 disposed below the thirdbonding pads may also be disposed, and the third conductive barrierlayer 442 and the third seed layer 442 may have an undercut structure,inwardly spaced apart from the outer periphery of each of the thirdbonding pads 445.

The second bonding pads 345 and the third bonding pads 445 may form anintermetallic interfacial bonding surface BS1. For example, the secondbonding pads 345 and the third bonding pads 4450 may be formed of thesame material (e.g., copper (Cu)), such that an interfacial surfacebetween the second bonding pads 345 and the third bonding pad 4450 maynot be distinct. As such, the second bonding pads 345 and the thirdbonding pads 445 may be bonded to each other using intermetallic bondinghaving strong bonding force, and accordingly, structural stability ofthe semiconductor package 500 may improve.

Also, the second insulating layer 341 of the second semiconductor chip300 may be in contact with the insulating layer 441 on the boundarybetween the second semiconductor chip 300 and the third semiconductorchip 400. In some example embodiments, the second insulating layer 341and the third insulating layer 441 may form inter-dielectric hybridbonding. For example, the second insulating layer 341 and the thirdinsulating layer 441 may be continuously formed, and the bonding surfaceB2 between the second insulating layer 341 and the third insulatinglayer 441 may not be visually distinct. For example, the secondinsulating layer 341 and the third insulating layer 441 may be formed ofthe same material (e.g., silicon oxide (SiO₂)), such that theinterfacial surface between the second insulating layer 341 and thethird insulating layer 441 may not be distinct.

As described above, the semiconductor package 500 according to exampleembodiments may have a structure in which different types of the firstsemiconductor chip 200, the second semiconductor chip 300, and the thirdsemiconductor chip 400 are stacked. Also, the stacking process may beimplemented by a wafer-on-wafer (WOW) method and also a wafer-on-diemethod.

In example embodiments, since the third semiconductor chip 400, whichmay be a logic chip, may generate a large amount of heat when beingdriven, the third semiconductor chip 400 may be disposed on an uppermostend. Also, a heat radiator 590 may be disposed on the rear surface 400 bof the third semiconductor chip 400. For example, the heat radiator 590may be attached to the third semiconductor chip 400 using an adhesivefilm (not illustrated). For example, the adhesive film (not illustrated)may include a thermal interfacial surface material (TIM) such as thermalgrease. The heat sink 550 may radiate heat generated from the stackstructure to the outside.

According to the aforementioned example embodiments, by forming thebonding pad in advance using a photoresist pattern and polishing thepassivation layer using a polishing stop film, a flat bonding surfacemay be formed, and a stack of the semiconductor chips having aninterfacial bonding surface having improved quality may be implemented.

While example embodiments have been illustrated and described above, itwill be apparent to those skilled in the art that modifications andvariations could be made without departing from the scope of the presentdisclosure as defined by the appended claims.

1. A semiconductor package, comprising: a first semiconductor chiphaving a first substrate, a first insulating layer on the firstsubstrate, and a plurality of first bonding pads on the first insulatinglayer, and having a flat upper surface by an upper surface of the firstinsulating layer and upper surfaces of the plurality of first bondingpads; and a second semiconductor chip on the upper surface of the firstsemiconductor chip and having a second substrate, a second insulatinglayer below the second substrate and in contact with the firstinsulating layer, and a plurality of second bonding pads on the secondinsulating layer and in contact with the first bonding pads,respectively, wherein the first insulating layer includes an insulatinginterfacial layer in contact with the second insulating layer, embeddedin the first insulating layer, and spaced apart from the plurality offirst bonding pads.
 2. The semiconductor package of claim 1, wherein adistance by which the insulating interfacial layer is spaced apart fromthe plurality of first bonding pads is in a range of 60% to 100% of athickness of each of the plurality of first bonding pads.
 3. Thesemiconductor package of claim 1, wherein the insulating interfaciallayer includes at least one of silicon nitride (SiN), silicon carbide(SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminumnitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), andaluminum oxide carbide (AlOC).
 4. The semiconductor package of claim 3,wherein at least one of the first insulating layer and the secondinsulating layer includes silicon oxide.
 5. The semiconductor package ofclaim 1, wherein the first semiconductor chip further includes: aprotective insulating film between the first substrate and the firstinsulating layer; through electrodes penetrating the first substrate andthe first insulating layer and connected to the plurality of firstbonding pads, respectively; and a conductive barrier layer and a seedlayer on the protective insulating film to be positioned in a regionbetween the plurality of first bonding pads and the through electrodes.6. The semiconductor package of claim 5, wherein the conductive barrierlayer and the seed layer are inwardly spaced apart from an outerperiphery of each of the plurality of first bonding pads.
 7. Thesemiconductor package of claim 6, wherein a distance by which each ofthe conductive barrier layer and the seed layer is spaced apart from theouter periphery of each of the plurality of first bonding pads is in arange of 1% to 15% of a width of each of the plurality of first bondingpads.
 8. The semiconductor package of claim 5, wherein the conductivebarrier layer includes at least one of titanium (Ti), titanium nitride(TiN), tantalum (Ta), and tantalum nitride (TaN), and the seed layerincludes Cu.
 9. The semiconductor package of claim 1, wherein each ofthe plurality of first bonding pads has an upwardly inclined sidesurface.
 10. The semiconductor package of claim 1, wherein the firstsemiconductor chip further includes a capping barrier film on a sidesurface of each of the plurality of first bonding pads.
 11. Thesemiconductor package of claim 10, wherein the capping barrier filmincludes at least one of silicon nitride (SiN), silicon carbide (SiC),silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride(AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), and aluminumoxide carbide (AlOC).
 12. The semiconductor package of claim 10, whereina thickness of the capping barrier film is in a range of 100 nm to 300nm.
 13. The semiconductor package of claim 10, wherein the cappingbarrier film includes a conductive material, and wherein the cappingbarrier film has a portion extending to an upper surface of each of theplurality of first bonding pads.
 14. The semiconductor package of claim13, wherein the capping barrier film includes at least one of coppersilicide (CuSix), titanium silicide (TiSix), CuSiN, cobalt (Co),tungsten (W), palladium (Pd), gold (Au), and nickel (Ni).
 15. Thesemiconductor package of claim 1, wherein the second insulating layerincludes an additional insulating interfacial layer in contact with thefirst insulating layer or the interfacial insulating layer, embedded inthe second insulating layer, and spaced apart from the plurality ofsecond bonding pads.
 16. A semiconductor package, comprising: a firstsemiconductor chip having a first substrate, a first insulating layer onthe first substrate, and a plurality of first bonding pads on the firstinsulating layer, and having a flat upper surface by an upper surface ofthe first insulating layer and upper surfaces of the plurality of firstbonding pads; and a second semiconductor chip on the upper surface ofthe first semiconductor chip and having a second substrate, a secondinsulating layer below the second substrate and in contact with thefirst insulating layer, and a plurality of second bonding pads on thesecond insulating layer and in contact with the first bonding pads,respectively, wherein the first semiconductor chip includes a protectiveinsulating film between the first substrate and the first insulatinglayer, through electrodes penetrating the first substrate and the firstinsulating layer and connected to the plurality of first bonding pads,respectively, and a first conductive barrier layer and a first seedlayer sequentially on the protective insulating film between theplurality of first bonding pads and the through electrodes, and whereinthe first conductive barrier layer and the first seed layer are inwardlyspaced apart from an outer periphery of each of the plurality of firstbonding pads.
 17. (canceled)
 18. The semiconductor package of claim 16,wherein the first conductive barrier layer includes at least one oftitanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalumnitride (TaN), and the first seed layer includes Cu.
 19. Thesemiconductor package of claim 16, wherein a thickness of the firstconductive barrier layer is in a range of 100 nm to 250 nm, and athickness of the first seed layer is in a range of 50 nm to 150 nm. 20.The semiconductor package of claim 16, wherein second semiconductor chipincludes an interlayer insulating film between the second substrate andthe plurality of second bonding pads, and a second conductive barrierlayer and a second seed layer sequentially on the interlayer insulatingfilm and below the plurality of second bonding pads, and wherein thesecond conductive barrier layer and the second seed layer are inwardlyspaced apart from an outer periphery of each of the plurality of secondbonding pads.
 21. A semiconductor chip, comprising: a substrate having afirst surface having an active region and a second surface opposite tothe first surface; an interlayer insulating film on the first surface ofthe substrate and having a wiring structure electrically connected tothe active region; a first passivation layer on the interlayerinsulating film and having first bonding pads electrically connected tothe wiring structure; a protective insulating film on the second surfaceof the substrate; through electrodes electrically connected to thewiring structure and penetrating the substrate and the protectiveinsulating film; a second passivation layer on the protective insulatingfilm and having second bonding pads electrically connected to thethrough electrode, wherein each of the second bonding pads has a widthincreasing toward the second surface of the substrate; and a conductivelayer on the protective insulating film to be positioned in a regionbetween the second bonding pads and the through electrodes, and inwardlyspaced apart from an outer periphery of each of the second bonding pads.22.-27. (canceled)